Miniaturization of portable consumer products such as MP3 players, mobile phones, digital camera are driving the need for smaller size packages with high memory density and more functionality. In response to the above-mentioned requirements, 3D style packages are preferred due to their shorter electrical connections. 3D packaging can be achieved with, for example, Through Silicon Via (TSV) technology which is applicable to wafer-to-wafer stacking or chip-to-wafer staking. However, reflow is required for the devices at each stack level and the reflow equation is “n” times reflow for “n” stacked package. For example, three times of reflow are necessary if three devices are stacked on top of an interposer substrate.
Conventional stacking process involves repeated handling of thin wafer. Since the thin wafers are delicate, the repeated handling of such wafers increases the potential for cracking, incurring high yield loss are of high possibility. Moreover, conventional methods used for forming stacked package encounter major thermal challenges as the existence of thermal hot spots might drastically affect the functionality of the device. Additionally, expensive equipment is needed to achieve wafer-to-wafer or chip-to-wafer stacking.
From the foregoing discussion, it is desirable to produce high thermal performance semiconductor package with low production cost and improved throughput. It is also desirable to produce semiconductor packages using existing assembly equipment and yet provides a robust thermally enhanced stacked semiconductor packaging.